The present invention relates to a multi-processor system and method for controlling an access to a page descriptor for paging, and more particularly to a multi-processor system and method for controlling an access to a page descriptor which is being reset (e.g., updated).
Paging systems use fixed-length blocks called "pages" and assign the pages to fixed regions of physical memory called "page frames". Referring to FIG. 1, each logical address comprises two parts: a page address and a displacement. The displacement is a relative address in a page. For each logical page address, there is the corresponding physical address of a page frame in main or secondary memory. A page table stores page descriptors specifying pages. Each page descriptor has a physical page address. Each physical address (e.g., effective address) comprises the physical page address and the displacement.
In a conventional multi-processor system with paging, while a page descriptor is updated by a certain processor, an access to the page descriptor by other processors is prohibited. Moreover, during the updating process and prior to performing other processes, the other processors must wait for completion of the updating, for example, by performing a loop of "firmware" instructions.
However, normal operations cannot be performed until the updating operation of the page descriptor is completed, since the other processors are in "waiting" (pause) states. This waiting by the other processors lowers the system performance since the other processors are idle.